1. Field of the Invention
This invention relates to a semiconductor memory device formed on a semiconductor substrate, and more particularly to a semiconductor memory device with an input/output terminal used both as a data input terminal and as a data output terminal.
2. Description of the Related Art
Random access memories (RAM) which allow data be read from or written into storage location thereof are widely used as large capacity data-storage devices by which the access time of the processor can be made rapid. It has been practiced in such a RAM that both of data input and output are performed through a common data input/output (I/O) terminal from the viewpoint of minimizing the number of external terminals and coordinating connections to external data bus. A data I/O terminal is connected commonly to a data input circuit and to a data output circuit. The data input circuit is activated in response to an active level of an external write enabling signal (WE). As a result, a write operation is commenced by supplying a data having a logic level to a designated address in the memory cell array. On the contrary, the data output circuit is activated when a supplied read enable signal (OE) is at its active level and a simultaneously supplied write enable signal (WE) is at its inactive level, and thus the data is readout from a designated address of the memory cell array through the data I/O terminal.
In the above-mentioned RAM, the data input circuit is controlled merely by the state of the write enable signal (WE). During write operation, the active level of write enable signal (WE) disenables the data output circuit so that, even if read enable signal (OE) changes to active level, readout operation is never executed. This ensures that external data level applied to the I/O terminal is prevented from getting abnormal condition which may be caused by the readout data from the RAM.
During the readout operation, however, the data input circuit is not disenabled by read enable signal (OE). Both at inactive level of write enable signal (WE) and at active level of read enable signal (OE), the prevention of data at the input/output terminal I/O from unexpectedly being written into the RAM is attained only under the use condition that write enable signal (WE) is not allowed to change to the active level until read enable signal (OE) changes again to the inactive level to complete the readout operation.
Disadvantage, however, still remains in this RAM in driving external load at a high speed. When the data output circuit drives the external load coupled to the data I/O terminal, a large operating current inevitably flows therethrough. For example, when the output data at the data I/O terminal is to be changed from a "high" level to a "low" level an output transistor in an output stage of the data output circuit engages for discharging the electric charges at the data I/O terminal to ground level. A large amount of operating current causes in the data output circuit to flow through an internal power line or internal ground line in the RAM, causing a transient variation in their power potentials. On the other hand, the write enable signal having the so-called TTL level of relatively small amplitude is supplied to the input circuit, and a determination result of its logic level is produced therefrom in the so-called MOS level which is used in the RAM. Also this input circuit is connected, in the RAM, to the internal power and ground lines which are, as mentioned earlier, connected to the output circuit. Accordingly, variation in potential of the power line and the ground line resulting from the operating current of the output circuit is directly applied to the input circuit, causing an erroneous operation of the input circuit. For example, drive of the data I/O terminal from "high" level to "low" level by the output circuit causes electric current to flow to the internal ground line through the output circuit, with effect of a rise in the potential of the internal ground line. In this case, under the affection by the risen ground potential applied to the input circuit, assuming that the write enable signal is at "high" (inactive) level, the input circuit erroneously recognizes the write enable signal actually having a high level to be a "low" level, resulting, in turn, in the operation of the data input circuit during readout operation, in confliction between the data input circuit and the data output circuit, and after all in erroneous operation of the RAM.